A Feature Extractor IC for Acoustic Emission Non-destructive Testing

In this paper, we present the design and the implementation of a digital Application Specific Integrated Circuit (ASIC) for Acoustic Emission (AE) non-destructive testing. The AE non-destructive testing method is a diagnostic method used to detect faults in mechanically loaded structures and components. If a structure is subjected to mechanical load or stress, the presence of structural discontinuities releases energy in the form of acoustic emissions through the constituting material. The analysis of these acoustic emissions can be used to determine the presence of faults in several structures. The proposed circuit has been designed for IoT (Internet of Things) applications, and it can be used to simplify the existing procedures adopted for structural integrity verifications of pressurized metal tanks that, in some countries, they are based on periodic checks. The proposed ASIC is provided of Digital Signal Processing (DSP) capabilities for the extraction of the main four parameters used in the AE analysis that are the energy of the signal, the duration of the event, the number of the crossing of a certain threshold and finally the maximum value reached by the AE signal. The circuit is provided of an SPI interface capable of sending and receiving data to/from wireless transceivers to share information on the web. The DSP circuit has been coded in VHDL and synthesized in 90 nm technology using Synopsys. The circuit has been characterized in terms of area, speed, and power consumption. Experimental results show that the proposed circuit presents very low power consumption properties and low area requirements

FPGA Implementation of Hand-written Number Recognition Based on CNN

Convolutional Neural Networks (CNNs) are the state-of-the-art in computer vision for different purposes such as image and video classification, recommender systems and natural language processing. The connectivity pattern between CNNs neurons is inspired by the structure of the animal visual cortex. In order to allow the processing, they are realized with multiple parallel 2-dimensional FIR filters that convolve the input signal with the learned feature maps.  For this reason, a CNN implementation requires highly parallel computations that cannot be achieved using traditional general-purpose processors, which is why they benefit from a very significant speed-up when mapped and run on Field Programmable Gate Arrays (FPGAs). This is because FPGAs offer the capability to design full customizable hardware architectures, providing high flexibility and the availability of hundreds to thousands of on-chip Digital Signal Processing (DSP) blocks. This paper presents an FPGA implementation of a hand-written number recognition system based on CNN. The system has been characterized in terms of classification accuracy, area, speed, and power consumption. The neural network was implemented on a Xilinx XC7A100T FPGA, and it uses 29.69% of Slice LUTs, 4.42% of slice registers and 52.50% block RAMs. We designed the system using a 9-bit representation that allows for avoiding the use of DSP. For this reason, multipliers are implemented using LUTs. The proposed architecture can be easily scaled on different FPGA devices thank its regularity. CNN can reach a classification accuracy of 90%

an automatic aw som vhdl ip core generator

In this paper, the authors present a MATLAB IP generator for hardware accelerators of All-Winner Self-Organizing Maps (AW-SOM). AW-SOM is a modified version of Kohonen's Self Organizing Maps (SOM) algorithm, which is one of the most used Machine Learning algorithms for data clustering, and vector quantization. The architecture of the AW-SOM method is meant for hardware implementations, and its main feature is a processing speed almost independent to the number of neurons since each of them is processed in a parallel way; the parallelization can be easily exploited by hardware custom hardware designs. The IP generator is built-in MATLAB and provides the user with the possibility to design a custom and efficient hardware accelerator. Several settings can be set such as the number of features and the number of neurons. The target language is the VHSIC Hardware Description Language (VHDL). The generated IP cores can be used for the training of the model and a built-in function of the software can also check the clustering performances using its inference capabilities. The accelerators produced by the software have been also characterized in terms of max frequency, hardware resources, and power consumption. The authors performed the hardware implementations on a XILINX Virtex 7 xc7vx690t FPGA

A Feature Extractor IC for Acoustic Emission Non-destructive Testing

In this paper, we present the design and the implementation of a digital Application Specific Integrated Circuit (ASIC) for Acoustic Emission (AE) non-destructive testing. The AE non-destructive testing method is a diagnostic method used to detect faults in mechanically loaded structures and components. If a structure is subjected to mechanical load or stress, the presence of structural discontinuities releases energy in the form of acoustic emissions through the constituting material. The analysis of these acoustic emissions can be used to determine the presence of faults in several structures. The proposed circuit has been designed for IoT (Internet of Things) applications, and it can be used to simplify the existing procedures adopted for structural integrity verifications of pressurized metal tanks that, in some countries, they are based on periodic checks. The proposed ASIC is provided of Digital Signal Processing (DSP) capabilities for the extraction of the main four parameters used in the AE analysis that are the energy of the signal, the duration of the event, the number of the crossing of a certain threshold and finally the maximum value reached by the AE signal. The circuit is provided of an SPI interface capable of sending and receiving data to/from wireless transceivers to share information on the web. The DSP circuit has been coded in VHDL and synthesized in 90 nm technology using Synopsys. The circuit has been characterized in terms of area, speed, and power consumption. Experimental results show that the proposed circuit presents very low power consumption properties and low area requirements

Energy Consumption Saving in Embedded Microprocessors Using Hardware Accelerators

This paper deals with the reduction of power consumption in embedded microprocessors. Computing power and energy efficiency are becoming the main challenges for embedded system applications. This is, in particular, the caseof wearable systems. When the power supply is provided by batteries, an important requirement for these systems is the long service life. This work investigates a method for the reduction of microprocessor energy consumption, based on the use of hardware accelerators. Their use allows to reduce the execution time and to decrease the clock frequency, so reducing the power consumption. In order to provide experimental results, authors analyze a case of study in the field of wearable devices for the processing of ECG signals. The experimental results show that the use of hardware accelerator significantly reduces the power consumption

fpga implementation of hand written number recognition based on cnn

Convolutional Neural Networks (CNNs) are the state-of-the-art in computer vision for different purposes such as image and video classification, recommender systems and natural language processing. The connectivity pattern between CNNs neurons is inspired by the structure of the animal visual cortex. In order to allow the processing, they are realized with multiple parallel 2-dimensional FIR filters that convolve the input signal with the learned feature maps. For this reason, a CNN implementation requires highly parallel computations that cannot be achieved using traditional general-purpose processors, which is why they benefit from a very significant speed-up when mapped and run on Field Programmable Gate Arrays (FPGAs). This is because FPGAs offer the capability to design full customizable hardware architectures, providing high flexibility and the availability of hundreds to thousands of on-chip Digital Signal Processing (DSP) blocks. This paper presents an FPGA implementation of a hand-written number recognition system based on CNN. The system has been characterized in terms of classification accuracy, area, speed, and power consumption. The neural network was implemented on a Xilinx XC7A100T FPGA, and it uses 29.69% of Slice LUTs, 4.42% of slice registers and 52.50% block RAMs. We designed the system using a 9-bit representation that allows for avoiding the use of DSP. For this reason, multipliers are implemented using LUTs. The proposed architecture can be easily scaled on different FPGA devices thank its regularity. CNN can reach a classification accuracy of 90%

Comparison between Trigonometric, and traditional DDS, in 90 nm technology

The Direct Digital frequency Synthesizer (DDS) is an architecture largely used for the generation of numeric sine and/or cosine waveforms in different applications. In this work, authors compare two different DDS architectures: the traditional architecture, based on the exploitation of quarter wave symmetry, and the Symon’s DDS (trigonometric DDS) presented in 2002. The two layout configurations have been implemented in 90 nm technology and compared in terms of area, speed and power consumption. Comparisons have been performed in terms of circuital complexity on architectures having the same Spurious Free Dynamic Range (SFDR) and phase resolution. Experiments show that the trigonometric architecture is very efficient in terms of area

Un database europeo INSPIRE-compliant per migliorare la resilienza dei beni culturali

L'insieme di leggi, azioni e organizzazioni per la tutela dei Beni Culturali (Cultural Heritage) nasce nei diversi paesi dell'Unione Europea dalle situazioni culturali locali, dove la capacità di far fronte all'emergenza è sicuramente diversa. Oltre ai danni che possono verificarsi ai beni culturali dopo un disastro, un intervento di emergenza inadeguato può a volte causare ulteriori perdite al CH. L'efficacia della risposta dipende dall'adeguatezza dell’approfondimento in fase di pianificazione. Alcuni paesi hanno progettato piani di emergenza ma i loro database (DB) sono frammentati, incompleti e non standardizzati. È quindi necessario stabilire un DB per l'assistenza di emergenza e mappe di CH a rischio da confrontare con mappe di rischi e rischi naturali, al fine di adottare misure preventive e operative, nonché concordare una terminologia comune e standard internazionali. Il progetto mira a migliorare la capacità della Protezione Civile di prevenire gli impatti dei disastri sul CH implementando una banca dati europea interoperabile (European Interoperable Database, EID) come strumento di supporto alle decisioni per comprendere il rischio di danni ai beni culturali. L'EID, a partire dagli standard internazionali per rappresentare gli oggetti della mappa (CityGML, INSPIRE), la classificazione di CH in Europa (UNESCO), in Italia (MiBACT), in Germania e in Francia e dall'analisi dei rischi e dei disastri, ha progettato, con il suo modello concettuale di dati, un'estensione del modello UML di INSPIRE. Questo DB supporterà anche modelli 3D per aiutare a trovare e riconoscere le opere disperse e facilitare un restauro post-emergenza, preservando così una memoria digitale in caso di distruzione

Search for dark matter produced in association with bottom or top quarks in √s = 13 TeV pp collisions with the ATLAS detector

A search for weakly interacting massive particle dark matter produced in association with bottom or top quarks is presented. Final states containing third-generation quarks and miss- ing transverse momentum are considered. The analysis uses 36.1 fb−1 of proton–proton collision data recorded by the ATLAS experiment at √s = 13 TeV in 2015 and 2016. No significant excess of events above the estimated backgrounds is observed. The results are in- terpreted in the framework of simplified models of spin-0 dark-matter mediators. For colour- neutral spin-0 mediators produced in association with top quarks and decaying into a pair of dark-matter particles, mediator masses below 50 GeV are excluded assuming a dark-matter candidate mass of 1 GeV and unitary couplings. For scalar and pseudoscalar mediators produced in association with bottom quarks, the search sets limits on the production cross- section of 300 times the predicted rate for mediators with masses between 10 and 50 GeV and assuming a dark-matter mass of 1 GeV and unitary coupling. Constraints on colour- charged scalar simplified models are also presented. Assuming a dark-matter particle mass of 35 GeV, mediator particles with mass below 1.1 TeV are excluded for couplings yielding a dark-matter relic density consistent with measurements